DRAM Layout Engineer: Design & Verification Expert

micron

Xalisco

Presencial

MXN 670.000 - 1.339.000

Jornada completa

14 días+
Generador de candidaturas

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Supera los filtros ATS

Descripción de la vacante

Micron Technology is seeking a DRAM Layout Engineer to translate schematics into physical IP layouts for DRAM chips. You will verify layouts, optimize area and routing, and ensure timely delivery across global teams.

The role requires 3+ years of CMOS layout experience, strong problem-solving, and proficiency with Cadence Virtuoso, Calibre, and Mentor tools. You will collaborate with design groups worldwide to meet project milestones.

Formación

  • Bachelor’s degree or equivalent in Electrical/Electronics/Mechatronics/Robotics/BME.
  • 3+ years of layout design experience in advanced CMOS processes.
  • Experience with IP layout development and physical verification.
  • Expertise in layout area, routing, rules, yield and reliability.
  • Knowledge of schematics, CAD collaboration.
  • Understanding layout effects on speed, power and area.
  • Strong problem-solving for layout verification.
  • Proficiency with Cadence Virtuoso, Calibre, and Mentor tools.

Responsabilidades

  • Design and development of IP layouts for DRAM chips.
  • Perform layout verification (LVS/DRC/EM) and maintain docs.
  • Ensure on-time delivery of block-level layouts with quality.
  • Lead planning, estimation, scheduling, delegation and execution.
  • Contribute to effective project management.
  • Plan layouts and present material for global reviews.
  • Coordinate with teams in India, Japan, US and elsewhere.

Conocimientos

Layout design
Team collaboration
Problem solving
Leadership
AI usage

Educación

Bachelor’s degree in Electrical/Electronics/Mechatronics/Robotics/BME

Herramientas

Cadence tools
Virtuoso
Calibre
Mentor tools

Descripción del empleo

Micron Technology is seeking a DRAM Layout Engineer to translate schematics into physical IP layouts for DRAM chips. You will verify layouts, optimize area and routing, and ensure timely delivery across global teams.

The role requires 3+ years of CMOS layout experience, strong problem-solving, and proficiency with Cadence Virtuoso, Calibre, and Mentor tools. You will collaborate with design groups worldwide to meet project milestones.

Consigue la evaluación confidencial y gratuita de tu currículum.

o arrastra y suelta tu archivo aquí

Similar jobs

Puestos de trabajo similares que vale la pena comparar

DRAM Layout Engineer — Lead IP Design & Verification
DRAM Layout Engineer — Lead IP Design & Verification

micron • Xalisco

Presencial
MXN 420.000 - 540.000
DRAM Layout Engineer: IP Block Design & Verification
DRAM Layout Engineer: IP Block Design & Verification

Micron Technology • Jalisco

Presencial
MXN 480.000 - 720.000
DRAM Design Layout Engineer (IP & Verification)
DRAM Design Layout Engineer (IP & Verification)

Micron Technology, Inc • Tlaquepaque

Híbrido
MXN 350.000 - 550.000
Medical plan
Dental plan
Vision plan
+2
DRAM Layout Design Engineer – IP Layout & Verification Lead
DRAM Layout Design Engineer – IP Layout & Verification Lead

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. • Jalisco

Presencial
MXN 867.603 - 1.388.165
DRAM Layout Engineer: Lead IP Layout & Verification
DRAM Layout Engineer: Lead IP Layout & Verification

Micron Technology, Inc • Tlaquepaque

Presencial
MXN 1.214.644 - 1.561.686
Medical, dental, and vision plans
Paid family leave
Paid time-off and holidays
DRAM Design Tech Layout Engineer
DRAM Design Tech Layout Engineer

Micron Technology • Tlaquepaque

Presencial
MXN 1.041.124 - 1.388.165
DRAM Layout Engineer Intern: Hands-on VLSI & EDA
DRAM Layout Engineer Intern: Hands-on VLSI & EDA

Micron Technology, Inc. • Tlaquepaque

Presencial
MXN 167.000 - 223.000
DRAM Design Technology Layout Engineer
DRAM Design Technology Layout Engineer

Micron Technology, Inc • Tlaquepaque

Presencial
MXN 693.962 - 1.040.943
Medical, dental, and vision plans
Paid family leave
Robust paid time-off program
+1
DRAM Layout Engineer: Analog & Digital Design
DRAM Layout Engineer: Analog & Digital Design

Micron • Jalisco

Presencial
MXN 134.000 - 201.000
DRAM Layout Design Engineer - CAD & Verification
DRAM Layout Design Engineer - CAD & Verification

Micron Technology, Inc • Tlaquepaque

Presencial
MXN 520.471 - 780.707
Medical, dental and vision plans
Paid family leave
Paid time-off program
+1