DRAM Layout Engineer — Lead IP Design & Verification

micron; Xalisco; Presencial; MXN 420.000 - 540.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. is seeking a senior DRAM layout engineer to translate schematics into IP layouts for DRAM chips and lead layout activities across global teams. You will verify layouts using LVS/DRC/EM and ensure on-time delivery with quality standards.

The role requires 3+ years in CMOS layouts, strong fundamentals in layout and routing, and deep Cadence/Mentor Calibre expertise. Collaboration with CAD and circuit teams is essential, enabling high-performance memory tech.

Formación

• 3+ years of experience in layout designs in advanced CMOS process.
• Experience with IP layout development and physical verification for complex designs.
• Expertise in layout area and routing optimization, design rules, yield and reliability issues.
• Strong understanding of layout fundamentals (electro-migration, latch-up, crosstalk, IR-drop, parasitic analysis).
• Knowledge of schematics, collaboration with circuit designers and CAD team.
• Understanding layout effects on speed, capacitance, power and area.
• Proficient with Cadence tools (Virtuoso) and Mentor Calibre; device matching and parasitic analysis.
• Leadership qualities and ability to multi-task; guide teammates.

Responsabilidades

• Design and development of IP layouts for DRAM chips.
• Perform layout verification (LVS/DRC/EM) and documentation.
• Ensure on-time delivery of block-level layouts with quality.
• Demonstrate leadership in planning, area/time estimation, scheduling and execution.
• Guide and mentor sub block-level layout developers.
• Contribute to effective project-management.
• Plan and detail layouts for global review.
• Coordinate with engineering teams across India, Japan, and the US.

Conocimientos

Leadership

Problem solving

Teamwork

Communication

Multi-tasking

Schematic collaboration

Educación

BE/BTech or MTech in Electronic/VLSI Engineering or equivalent

Diploma in Electronic or VLSI engineering

Herramientas

Cadence Virtuoso

Cadence Layout XL

Mentor Calibre

Device Matching

Parasitic Analysis

Electron Migration

Descripción del empleo

Micron Technology, Inc. is seeking a senior DRAM layout engineer to translate schematics into IP layouts for DRAM chips and lead layout activities across global teams. You will verify layouts using LVS/DRC/EM and ensure on-time delivery with quality standards.

The role requires 3+ years in CMOS layouts, strong fundamentals in layout and routing, and deep Cadence/Mentor Calibre expertise. Collaboration with CAD and circuit teams is essential, enabling high-performance memory tech.