Lead Analog/Mixed-Signal Layout Engineer

Micron Technology; Tlaquepaque; Presencial; MXN 420.000 - 620.000; Jornada completa

Descripción de la vacante

Micron Technology in Guadalajara, Mexico is seeking a Layout Build Engineer for its DRAM team. You will work on analog, mixed-signal, and full-chip layout across multiple projects, collaborating with global teams to meet schedules and quality targets.

You should have about 5 years in analog/custom layout in CMOS processes, BE or MTech in Electronic/VLSI, and hands-on Cadence VLE/VXL and Calibre. The role offers challenging opportunities in AI and HPC applications.

Formación

• Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in planar and FinFET nodes.
• BE or MTech in Electronic/VLSI Engineering, or related.
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS.
• Hands-on experience creating layout for critical blocks like Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, and Differential Amplifier.
• Knowledge of analog layout fundamentals and layout effects on speed, capacitance, power and area.
• Ability to understand design constraints and implement high-quality layouts.

Responsabilidades

• Build and development of analog, mixed-signal, custom digital blocks and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Lead planning, area/time estimation, scheduling, delegation and execution across multiple projects.
• Collaborate with global engineering teams to ensure layout project success.

Conocimientos

Analog Layout

Custom Layout

CMOS Process

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Block-level Layout

Leadership

Educación

BE or MTech in Electronic/VLSI Engineering

Herramientas

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Descripción del empleo

Micron Technology in Guadalajara, Mexico is seeking a Layout Build Engineer for its DRAM team. You will work on analog, mixed-signal, and full-chip layout across multiple projects, collaborating with global teams to meet schedules and quality targets.

You should have about 5 years in analog/custom layout in CMOS processes, BE or MTech in Electronic/VLSI, and hands-on Cadence VLE/VXL and Calibre. The role offers challenging opportunities in AI and HPC applications.