Analog Ic Design Engineer

Whatjobs; Pisa; In loco; EUR 60.000 - 80.000; Tempo pieno

Descrizione del lavoro

A growing technology company is seeking a Senior Analog IC Design Engineer to design and develop high-speed PLLs and implement on-chip power management circuits. The ideal candidate will have a proven background in PLL and power management design, expertise in CMOS analog fundamentals, and collaboration skills. This role offers a chance to work on cutting-edge technologies in a dynamic environment located in Italy, Tuscany, Pisa.

Competenze

• Proven experience in PLL and power management design, ideally at or near 12nm nodes.
• Strong background in CMOS analog design fundamentals.
• Detail-oriented with excellent problem-solving skills.

Mansioni

• Design and develop high-speed PLLs (10 GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate with digital, systems and photonic teams on mixed signal integration.
• Run simulations, oversee layout and verify performance of analog building blocks.
• Bring industry trends and design innovations into the development cycle.

Conoscenze

High-speed PLL design

Power management circuit implementation

Collaboration with teams

Simulation and layout oversight

Problem solving skills

Strumenti

Cadence

Spectre

Descrizione del lavoro

I am recruiting for a Senior Analog IC Design Engineer on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position is focused on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineer will contribute to cutting-edge developments in energy-efficient interconnects.

Key Responsibilities

• Design and develop high-speed PLLs (10 GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate closely with digital, systems and photonic teams on complex mixed signal integration
• Run simulations, oversee layout and verify performance of analog building blocks
• Bring industry trends and design innovations into the development cycle

Required Experience

• Proven track record in PLL and power management design, ideally at or near 12nm nodes
• Strong background in CMOS analog design fundamentals
• Proficient with tools like Cadence and Spectre
• Detail oriented with excellent problem solving skills

To be considered for this opportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.