Senior Digital Verification Engineer - Power ICs

Allegro MicroSystems; Musselburgh; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading semiconductor company is seeking a Digital Verification Engineer to join their Design Centre in Edinburgh or Milan. This role involves developing comprehensive verification plans, creating UVM-based environments, and analyzing test results. The ideal candidate will have a Bachelor's degree in Electrical Engineering and experience with System Verilog and mixed-signal testbenches. This position offers a dynamic work environment with a focus on quality and collaboration.

Qualifications

• Knowledge of embedded SoC design and verification life-cycle.
• Experience with regression testing and debugging design behavior.
• Capable of building mixed-signal testbenches and checkers.

Responsibilities

• Develop comprehensive verification plans based on specifications.
• Create and maintain UVM-based verification environments.
• Analyze and debug unexpected design behavior.

Skills

System Verilog

Verilog

UVM/OVM

C/C++

Python

Debugging

Education

Bachelor's degree in Electrical and/or Electronic Engineering

Tools

SystemVerilog

Verilog-AMS

Job description

A leading semiconductor company is seeking a Digital Verification Engineer to join their Design Centre in Edinburgh or Milan. This role involves developing comprehensive verification plans, creating UVM-based environments, and analyzing test results. The ideal candidate will have a Bachelor's degree in Electrical Engineering and experience with System Verilog and mixed-signal testbenches. This position offers a dynamic work environment with a focus on quality and collaboration.