ASIC Digital Design Engineer

Synopsys, Inc.; Brackley; On-site; GBP 100,000 - 125,000; Full time

Job summary

A leading semiconductor company is seeking a passionate ASIC Digital Design professional in Brackley. You will lead DFT methodologies, focusing on scan insertion, ATPG flows, and addressing design challenges. Join a collaborative and innovative team driving technological advancements in AI and automotive sectors. Expected qualifications include extensive DFT experience and proficiency in relevant EDA tools. An inclusive culture fostering mentorship is integral to our operations.

Benefits

Comprehensive health benefits

Wellness programs

Financial benefits

Qualifications

• Extensive hands-on experience with DFT methodologies for complex ASIC designs.
• Proficiency in industry-standard EDA tools like Spyglass DFT and scan STA analysis.
• Strong understanding of digital logic design and verification principles.

Responsibilities

• Lead and execute scan insertion and ATPG flows for ASIC designs.
• Work closely with RTL and Verification teams for early integration of DFT.
• Analyze and resolve DFT-related issues using tools like Spyglass DFT.

Skills

Design-for-Testability methodologies

Scan insertion

ATPG

Scan STA

Scripting (TCL, Perl, Python)

Tools

Spyglass DFT

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.

What You’ll Be Doing:

• Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.
• Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
• Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
• Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
• Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.
• Contribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.

The Impact You Will Have:

• Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.
• Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization.
• Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.
• Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.
• Empower cross-functional teams by sharing expertise, fostering a culture of continuous improvement and collaboration.
• Contribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.

What You’ll Need:

• Extensive hands-on experience with DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
• Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
• Strong understanding of digital logic design, RTL coding, and verification principles.
• Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
• Solid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.

Who You Are:

• Collaborative team player who communicates effectively across functions and cultures.
• Proactive problem solver, comfortable with ambiguity and rapid change.
• Detail-oriented and highly organized, with a commitment to delivering high-quality results.
• Inclusive and open-minded, eager to share knowledge and mentor others.
• Self-motivated and driven by curiosity, with a continuous learning mindset.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative DFT team within Synopsys’ Engineering organization in Bangalore. The team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.