Senior Digital Verification Lead (UVM/Xcelium)

Cadence Design Systems, Inc.; Cesson-Sévigné; Hybrid; EUR 90,000 - 125,000; Full time

Benefits offered by this job

Meal vouchers

Remote work days

Great Place to Work certification

Job summary

Cadence Design Systems, Inc. in France (Rennes/Paris) seeks a Senior Digital Verification Engineer to lead the development and execution of robust UVM verification environments for high‑performance ASIC designs.

You will drive verification strategy, automate large‑scale regression, and mentor a team across cross‑functional groups. The role requires 7–10 years in digital verification, strong SystemVerilog/UVM skills, Cadence Xcelium expertise, and hands‑on experience with constrained‑random and

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 7–10 years of professional digital verification experience, including ≥ 5 years with UVM on ASIC or FPGA projects.
• Proficiency in SystemVerilog/UVM.
• Strong hands‑on experience with Cadence Xcelium.
• Knowledge of synthesis‑aware verification (constraint‑driven random, coverage‑driven).
• Deep understanding of functional coverage, assertions (SVA), formal verification, and constrained‑random verification.
• Excellent communication, problem‑solving, and leadership capabilities.

Responsibilities

• Define and implement robust, scalable UVM test‑bench architectures for complex digital IPs.
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models).
• Develop directed, random, and constrained‑random test cases to achieve 100% functional coverage on target designs.
• Lead root‑cause analysis of simulation failures and silicon bring‑up bugs.
• Coordinate with design teams to close verification gaps before RTL freeze.
• Contribute to internal verification guidelines, templates, and training materials.
• Mentor junior verification engineers (T1‑T3) and provide technical guidance on UVM and debugging.
• Participate in design/verification reviews with constructive feedback.

Skills

SystemVerilog/UVM

Cadence Xcelium

Digital verification

UVM testbenches

Code coverage

Mentoring

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

Python

TCL

Makefile

Bash

Git

CI/CD

Job description

Cadence Design Systems, Inc. in France (Rennes/Paris) seeks a Senior Digital Verification Engineer to lead the development and execution of robust UVM verification environments for high‑performance ASIC designs.

You will drive verification strategy, automate large‑scale regression, and mentor a team across cross‑functional groups. The role requires 7–10 years in digital verification, strong SystemVerilog/UVM skills, Cadence Xcelium expertise, and hands‑on experience with constrained‑random and