Remote Senior Digital Verification Engineer

Cadence; Paris; Híbrido; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Competitive salary

Meal vouchers

Remote work days

Great Place to Work

Volunteer days

Office Rennes/Paris

CSE benefits

Descripción de la vacante

Cadence seeks a Senior Digital Verification Engineer to lead UVM verification for high-performance ASIC designs. You will build scalable verification environments, mentor junior engineers, and collaborate with design and software teams to ensure first-silicon success.

You will drive automated regression, optimize test-bench architectures, and contribute to verification guidelines while leveraging Cadence tools across locations in France (Rennes/Paris) with some remote days.

Formación

• B.S. or M.S. in Electrical/Computer Engineering or related field.
• 7–10 years of professional digital verification experience, including ≥5 years with UVM on ASIC or FPGA projects.
• Proficiency in SystemVerilog/UVM.
• Strong hands-on experience with Cadence Xcelium.
• Knowledge of synthesis-aware verification, coverage-driven closure.
• Excellent communication, problem-solving, and leadership capabilities.

Responsabilidades

• Define and implement robust, scalable UVM test-bench architectures for complex digital IPs.
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models).
• Develop directed, random, and constrained-random test cases to achieve coverage goals.
• Lead root-cause analysis of simulation failures and silicon issues.
• Coordinate with design teams to close verification gaps before RTL freeze.
• Mentor junior verification engineers (T1-T3).
• Participate in reviews and risk assessments.

Conocimientos

UVM

SystemVerilog

Cadence Xcelium

Python scripting

TCL scripting

Makefile/Bash

Git

CI/CD tools

VIP verification

Educación

B.S./M.S. in Electrical or Computer Engineering

Herramientas

Cadence Xcelium

Descripción del empleo

Cadence seeks a Senior Digital Verification Engineer to lead UVM verification for high-performance ASIC designs. You will build scalable verification environments, mentor junior engineers, and collaborate with design and software teams to ensure first-silicon success.

You will drive automated regression, optimize test-bench architectures, and contribute to verification guidelines while leveraging Cadence tools across locations in France (Rennes/Paris) with some remote days.