Tech Lead Verification Engineer

IC Resources; Auvergne-Rhône-Alpes; Hybride; EUR 85 000 - 110 000; Plein temps

Résumé du poste

IC Resources is seeking a senior ASIC/SoC verification engineer to lead verification strategy on complex projects, architect SystemVerilog/UVM environments and own verification plans.

You will stay hands-on with SystemVerilog, UVM, Python, SVA and Formal techniques, mentoring other verification engineers and driving automation across multiple semiconductor markets. The role offers a hybrid setup with remote options in the EU.

Qualifications

• 8+ years of ASIC/SoC verification experience.
• Strong hands-on knowledge of SystemVerilog/UVM/SVA/Formal techniques.
• Experience leading projects or mentoring engineers is important.

Responsabilités

• Lead verification strategy for complex ASIC, SoC and IP projects.
• Architect SystemVerilog / UVM verification environments.
• Own verification plans, coverage strategy and sign-off.
• Remain hands-on with SystemVerilog, UVM, Python, SVA and Formal Verification.
• Work with ARM, RISC-V, AXI/AHB/APB, CHI, PCIe, CXL and Ethernet.
• Mentor other Verification Engineers and act as a technical reference.
• Improve verification methodologies, automation and internal best practices.
• Contribute to internal R&D and technical innovation.

Connaissances

SystemVerilog

UVM

ASIC Verification

SoC Verification

Python

SVA

Formal Verification

Verification Planning

Coverage

RTL

Description du poste

What you'll be doing

• Lead verification strategy for complex ASIC, SoC and IP projects
• Architect SystemVerilog / UVM verification environments
• Own verification plans, coverage strategy and sign-off
• Remain hands-on with SystemVerilog, UVM, Python, SVA and Formal Verification
• Work with technologies including ARM, RISC-V, AXI, AHB, APB, CHI, PCIe, CXL and Ethernet
• Mentor other Verification Engineers and act as a technical reference point
• Improve verification methodologies, automation and internal best practices
• Contribute to internal R&D and technical innovation

What we're looking for

You'll ideally have 8+ years of ASIC / SoC Design Verification experience and strong hands-on knowledge of:

• SystemVerilog
• UVM
• ASIC Verification
• SoC Verification
• Python
• SVA
• Formal Verification
• Verification Planning
• Coverage
• RTL

Previous experience leading projects or mentoring engineers is important, although you don't need to be a people manager.

Why consider it?

This is not a role where you'll spend your career verifying the same block.You'll work alongside verification specialists on technically demanding projects across multiple semiconductor markets, while continuing to build your expertise through an extensive internal training library covering UVM, Formal, Verification Planning, AI and advanced verification techniques.The environment is technical, collaborative and genuinely engineering-led, with plenty of scope to influence how verification is done rather than simply follow an existing methodology.

Locations: France or Sweden

Working model: Flexible / hybrid with remote options depending on project

Eligibility: Applicants must already have the right to work in the EU