Senior Digital Verification Lead — UVM Expert Remote

Cadence; Cesson-Sévigné; Híbrido; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Remote work days

Offices in Rennes & Paris

Meal vouchers

Great Place to Work certified

Descripción de la vacante

Cadence in France is seeking a Senior Digital Verification Engineer to lead robust UVM test-benches for high-performance ASIC designs. You will drive verification strategy, automate large-scale regression flows, and mentor a growing team to ensure functional and code coverage targets.

You will collaborate with design and software groups, implement reusable verification components, and contribute to verification guidelines.

Formación

• Bachelor's or Master's degree in a relevant engineering field.
• 7–10 years of professional digital verification experience with UVM on ASIC/FPGA projects.
• Strong hands-on experience with Cadence Xcelium and SystemVerilog/UVM.

Responsabilidades

• Define and implement robust, scalable UVM test-bench architectures for complex digital IPs.
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models).
• Develop directed, random, and constrained-random test cases to achieve 100% functional coverage and 100% code coverage on target designs.
• Lead root-cause analysis of simulation failures, performance bottlenecks, and silicon bring-up bugs.
• Coordinate with design teams to close verification gaps before RTL freeze.
• Mentor junior verification engineers and provide technical guidance on UVM and test-bench design.
• Participate in design/verification reviews, providing constructive feedback and risk assessment.

Conocimientos

UVM verification

SystemVerilog

Leadership

Debugging

Problem-solving

Cross-functional collaboration

Educación

B.S. or M.S. in Electrical Engineering

Electrical/Computer Engineering

Herramientas

Cadence Xcelium

Python/TCL scripting

Descripción del empleo

Cadence in France is seeking a Senior Digital Verification Engineer to lead robust UVM test-benches for high-performance ASIC designs. You will drive verification strategy, automate large-scale regression flows, and mentor a growing team to ensure functional and code coverage targets.

You will collaborate with design and software groups, implement reusable verification components, and contribute to verification guidelines.