Senior HW Digital Design Verification Engineer

NXP Semiconductors NV

Valbonne

On-site

EUR 70,000 - 110,000

Full time

34 hours ago
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Job summary

NXP Semiconductors Netherlands B.V. is seeking a Senior HW Digital Design Verification Engineer to lead verification for complex ASIC/SoC blocks. You will define verification strategies, develop testbenches, and drive coverage closure with UVM and formal methods.

You will collaborate with design, architecture, and software teams, mentor engineers, and contribute to flow improvements while ensuring robust, high-quality digital designs across projects.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in digital design verification of complex ASICs/SoCs.
  • Strong proficiency in SystemVerilog and UVM.
  • Experience with formal verification techniques is a plus.
  • Solid understanding of digital design principles, computer architecture, and communication protocols.

Responsibilities

  • Develop and execute verification plans for complex digital blocks and subsystems, including testbench architecture, testcase development, and coverage closure.
  • Implement advanced verification methodologies such as UVM (Universal Verification Methodology) and formal verification techniques.
  • Create and maintain verification environments using industry-standard tools and languages (e.g., SystemVerilog, UVM, OVM, e).
  • Develop directed, constrained-random, and assertion-based testbenches to thoroughly validate design functionality and performance.
  • Perform functional and code coverage analysis to ensure verification completeness.
  • Debug complex design and verification issues, working closely with design engineers to identify root causes and propose solutions.
  • Collaborate with design, architecture, and software teams to understand design specifications and requirements.
  • Contribute to continuous improvement of verification methodologies, flows, and tools.
  • Mentor junior engineers and share technical expertise within the team.

Skills

Problem solving
Communication
Team collaboration

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or a related field

Tools

SystemVerilog
UVM
OVM
e language
Python
Waveform viewers
Coverage analysis tools

Job description

Job Summary

NXP Semiconductors Netherlands B.V. is seeking a highly skilled and experienced Senior HW Digital Design Verification Engineer to join our dynamic team. In this role, you will be responsible for defining and implementing comprehensive verification strategies for complex digital designs, ensuring the robustness and correctness of our cutting-edge semiconductor products.

Job Responsibilities
  • Develop and execute detailed verification plans for complex digital blocks and sub-systems, including testbench architecture, testcase development, and coverage closure.
  • Implement advanced verification methodologies such as UVM (Universal Verification Methodology) and formal verification techniques.
  • Create and maintain verification environments using industry-standard tools and languages (e.g., SystemVerilog, UVM, OVM, e).
  • Develop directed, constrained-random, and assertion-based testbenches to thoroughly validate design functionality and performance.
  • Perform functional and code coverage analysis to ensure verification completeness.
  • Debug complex design and verification issues, working closely with design engineers to identify root causes and propose solutions.
  • Collaborate with design, architecture, and software teams to understand design specifications and requirements.
  • Contribute to continuous improvement of verification methodologies, flows, and tools.
  • Mentor junior engineers and share technical expertise within the team.
Job Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in digital design verification of complex ASICs/SoCs.
  • Strong proficiency in SystemVerilog and UVM.
  • Demonstrated experience in developing comprehensive test plans and verification environments from scratch.
  • Solid understanding of digital design principles, computer architecture, and communication protocols.
  • Experience with industry-standard EDA verification tools (e.g., simulators, waveform viewers, coverage analysis tools).
  • Familiarity with scripting languages (e.g., Python, Perl, Tcl).
  • Experience with formal verification techniques is a plus.
  • Excellent problem-solving, analytical, and debugging skills.
  • Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.

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