Senior Digital Verification Engineer

Cadence; Cesson-Sévigné; Híbrido; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Remote work days

Offices in Rennes & Paris

Meal vouchers

Great Place to Work certified

Descripción de la vacante

Cadence in France is seeking a Senior Digital Verification Engineer to lead robust UVM test-benches for high-performance ASIC designs. You will drive verification strategy, automate large-scale regression flows, and mentor a growing team to ensure functional and code coverage targets.

You will collaborate with design and software groups, implement reusable verification components, and contribute to verification guidelines.

Formación

• Bachelor's or Master's degree in a relevant engineering field.
• 7–10 years of professional digital verification experience with UVM on ASIC/FPGA projects.
• Strong hands-on experience with Cadence Xcelium and SystemVerilog/UVM.

Responsabilidades

• Define and implement robust, scalable UVM test-bench architectures for complex digital IPs.
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models).
• Develop directed, random, and constrained-random test cases to achieve 100% functional coverage and 100% code coverage on target designs.
• Lead root-cause analysis of simulation failures, performance bottlenecks, and silicon bring-up bugs.
• Coordinate with design teams to close verification gaps before RTL freeze.
• Mentor junior verification engineers and provide technical guidance on UVM and test-bench design.
• Participate in design/verification reviews, providing constructive feedback and risk assessment.

Conocimientos

UVM verification

SystemVerilog

Leadership

Debugging

Problem-solving

Cross-functional collaboration

Educación

B.S. or M.S. in Electrical Engineering

Electrical/Computer Engineering

Herramientas

Cadence Xcelium

Python/TCL scripting

Descripción del empleo

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.

This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products-from chips to boards to systems-for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.

At Secure-IC, a Cadence company, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: T4 - Principal Design Engineer

Location: France, Rennes (preferably) or Paris

Reports to: Sr Design Engineering Manager

Job Overview: Senior Digital Verification Engineer

You will lead the development and execution of robust, reusable UVM verification environments for our products, ensuring functional - coverage and first - silicon success.

By driving verification strategy, automating large - scale regression flows, and mentoring the verification team, the role directly safeguards the quality of high - performance ASIC designs.

The work spans building scalable test - bench architectures, integrating Cadence verification tools, and collaborating cross - functionally with design and software teams to close verification gaps before RTL freeze.

Job Responsibilities:

• Define and implement robust, scalable UVM test - bench architectures for complex digital IPs
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models)
• Develop directed, random, and constrained - random test cases to achieve 100 % functional coverage and 100 % code coverage on target designs
• Lead root - cause analysis of simulation failures, performance bottlenecks, and silicon bring - up bugs
• Coordinate with design teams to close verification gaps before RTL freeze
• Contribute to internal verification guidelines, templates, and training materials
• Mentor junior verification engineers (T1 - T3) and provide technical guidance on UVM, test - bench design, and debugging techniques
• Participate in design/verification reviews, providing constructive feedback and risk assessment

Job Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 7 - 10 years of professional digital verification experience, including ≥ 5 years with UVM on ASIC or FPGA projects
• Proficiency in SystemVerilog/UVM
• Strong hands - on experience with Cadence Xcelium
• Knowledge of synthesis - aware verification (e.g., constraint - driven random verification, coverage - driven closure)
• Deep understanding of functional coverage, assertions (SVA), formal verification, and constrained - random verification
• Comfortable with large - scale simulation environments, waveform analysis, and performance profiling
• Excellent communication, problem - solving, and leadership capabilities
• Ability to influence cross - functional teams and mentor junior engineers.

Additional Skills/Preferences:

• Hands - on with verification IP (VIP) development and integration
• Exposure to low - power verification (e.g., power - aware UVM, clock gating checks)
• Scripting in Python, TCL, Makefile or Bash for automation
• Familiarity with Git and CI/CD tools

Check what we can offer you:

• An attractive compensation package, including a competitive salary, variable compensation, and meal vouchers
• A positive, stimulating, and supportive work environment
• Offices in France (Rennes and Paris) as well as internationally
• A dynamic and friendly company culture: after-work events, sports challenges, board games, pool table, foosball, and Nintendo Switch
• 5 days of paid leave dedicated to volunteering and community engagement, along with 7 "recharge days" (company-wide paid days off)
• The opportunity to join a company certified Great Place to Work® and ranked among the Fortune 100
• Remote work days
• Access to a CSE benefits platform, including discounts and gift cards

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Cadence est un leader clé dans le domaine de la conception électronique, s'appuyant sur plus de 30 ans d'expertise en logiciels de calcul. Nous appliquons notre stratégie de conception intelligente des systèmes (Intelligent System Design) pour fournir des logiciels, du matériel et des propriétés intellectuelles (IP) qui transfo