Senior Digital Verification Engineer — Lead UVM & 100% Coverage

Cadence Design Systems, Inc.; Rennes; Presencial; EUR 90.000 - 120.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Meal vouchers

Remote work days

Great Place to Work recognition

Descripción de la vacante

Cadence Design Systems, Inc. is seeking a Senior Digital Verification Engineer to lead robust UVM verification environments for high-performance ASIC designs.

You will drive verification strategy, automate large-scale regression flows, and mentor a verification team across cross-functional groups. Responsibilities include scalable test-bench architectures, reusable verification components, and achieving full functional and code coverage before RTL freeze.

Formación

• 7–10 years of professional digital verification experience
• ≥5 years with UVM on ASIC/FPGA projects
• Proficiency in SystemVerilog/UVM and Cadence Xcelium

Responsabilidades

• Define and implement robust, scalable UVM test-bench architectures for complex digital IPs
• Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models)
• Develop directed, random, and constrained-random tests to achieve full functional and code coverage
• Lead root-cause analysis of simulation failures and silicon bring-up issues
• Coordinate with design teams to close verification gaps before RTL freeze
• Mentor junior verification engineers (T1–T3) and provide technical guidance
• Participate in design/v erification reviews with constructive feedback and risk assessment

Conocimientos

UVM verification

SystemVerilog

Debugging

Leadership

Communication

Educación

Bachelor/Master in Electrical or Computer Engineering

Herramientas

Cadence Xcelium

Python/TCL scripting

Git & CI/CD

Descripción del empleo

Cadence Design Systems, Inc. is seeking a Senior Digital Verification Engineer to lead robust UVM verification environments for high-performance ASIC designs.

You will drive verification strategy, automate large-scale regression flows, and mentor a verification team across cross-functional groups. Responsibilities include scalable test-bench architectures, reusable verification components, and achieving full functional and code coverage before RTL freeze.