Senior Verification Engineer - UVM, SystemVerilog, SoC VIP

IC Resources

Grenoble

Sur place

EUR 50 000 - 70 000

Plein temps

14 jours+

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Résumé du poste

A leading semiconductor engineering firm is seeking a Senior Verification Engineer in Grenoble. This role involves R&D projects and developing verification environments using SystemVerilog and UVM. Candidates should have proven experience with verification processes and strong programming skills. Fluency in English is required, and French is preferred. This is an excellent opportunity to work in a friendly and growing environment with exciting projects.

Qualifications

  • Proven experience with IP or SoC verification.
  • Confident knowledge of SystemVerilog and UVM methodology.
  • Knowledge of AMBA / AXI communication protocols.

Responsabilités

  • Responsible for R&D projects and development of verification environments.
  • Develop VIP components and provide training to other engineers.

Connaissances

IP or SoC verification
SystemVerilog knowledge
UVM methodology
Bus communication protocols
Object Oriented Programming
Scripting skills (Perl, shell, Python, C)
Fluent English
French (preferable)

Description du poste

A leading semiconductor engineering firm is seeking a Senior Verification Engineer in Grenoble. This role involves R&D projects and developing verification environments using SystemVerilog and UVM. Candidates should have proven experience with verification processes and strong programming skills. Fluency in English is required, and French is preferred. This is an excellent opportunity to work in a friendly and growing environment with exciting projects.
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