Senior Verification Engineer - UVM, SystemVerilog, SoC VIP

IC Resources

Grenoble

On-site

EUR 50,000 - 70,000

Full time

14 days+

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

A leading semiconductor engineering firm is seeking a Senior Verification Engineer in Grenoble. This role involves R&D projects and developing verification environments using SystemVerilog and UVM. Candidates should have proven experience with verification processes and strong programming skills. Fluency in English is required, and French is preferred. This is an excellent opportunity to work in a friendly and growing environment with exciting projects.

Qualifications

  • Proven experience with IP or SoC verification.
  • Confident knowledge of SystemVerilog and UVM methodology.
  • Knowledge of AMBA / AXI communication protocols.

Responsibilities

  • Responsible for R&D projects and development of verification environments.
  • Develop VIP components and provide training to other engineers.

Skills

IP or SoC verification
SystemVerilog knowledge
UVM methodology
Bus communication protocols
Object Oriented Programming
Scripting skills (Perl, shell, Python, C)
Fluent English
French (preferable)

Job description

A leading semiconductor engineering firm is seeking a Senior Verification Engineer in Grenoble. This role involves R&D projects and developing verification environments using SystemVerilog and UVM. Candidates should have proven experience with verification processes and strong programming skills. Fluency in English is required, and French is preferred. This is an excellent opportunity to work in a friendly and growing environment with exciting projects.
Get your free, confidential resume review.

or drag and drop your file here.

TrustpilotImage showing a rating of 4.5 out of 5 stars on Trustpilot for JobLeads, indicating a high level of customer satisfaction.
Rated “Excellent” based on 23,878 reviews
Similar jobs

Similar jobs worth comparing

Ingénieur Vérification UVM Sénior SoC/ASIC – SystemVerilog
Ingénieur Vérification UVM Sénior SoC/ASIC – SystemVerilog

Elsys Design • Valbonne

On-site
EUR 40,000 - 60,000
10 jours de RTT par an
Allocation repas prise en charge
Mutuelle Santé Famille
+5
Senior RTL & UVM Verification Engineer, eFPGA IP
Senior RTL & UVM Verification Engineer, eFPGA IP

Menta SAS • Valbonne

On-site
EUR 45,000 - 70,000
Design Verification Engineer
Design Verification Engineer

IC Resources • Grenoble

On-site
EUR 50,000 - 70,000
SoC Verification Engineer - NOC & UVM Expert
SoC Verification Engineer - NOC & UVM Expert

IC Resources • Paris

On-site
EUR 65,000 - 90,000
Senior RTL Verification Engineer — SystemVerilog/UVM Expert
Senior RTL Verification Engineer — SystemVerilog/UVM Expert

Caraz • Valbonne

Hybrid
EUR 70,000 - 105,000
Ingénieur Vérification UVM pour SoC/ASIC FPGA (Remote)
Ingénieur Vérification UVM pour SoC/ASIC FPGA (Remote)

Elsys Design • Provence-Alpes-Côte d'Azur

On-site
EUR 45,000 - 65,000
Flex office
Télétravail
Activités sportives et ludiques
Vérification ASIC/SoC — SystemVerilog/UVM Expert
Vérification ASIC/SoC — SystemVerilog/UVM Expert

Atos • Échirolles

Hybrid
EUR 40,000 - 50,000
Télétravail partiel
Tickets resto
Congés
+3
Senior Digital Verification Engineer – ASIC/SoC Expert
Senior Digital Verification Engineer – ASIC/SoC Expert

NXP Semiconductors • Grenoble

Hybrid
EUR 85,000 - 110,000
Lead Architecte Vérification ASIC/SoC - UVM
Lead Architecte Vérification ASIC/SoC - UVM

Constencia • Valbonne

On-site
EUR 65,000 - 85,000
Contribuer à des projets à fort impact
Environnement collaboratif, agile et stimulant
Culture de la transparence et de l'excellence technique
+2
Ingénieur Vérification Numérique IP/SoC – SystemVerilog/UVM
Ingénieur Vérification Numérique IP/SoC – SystemVerilog/UVM

STMicroelectronics France • Grenoble

On-site
EUR 55,000 - 85,000
Similar jobs