Wireless PHY DV Engineer (Pre-Silicon) - SoC Verification

Apple Inc.; San Francisco (CA); Vor Ort; USD 123.000 - 214.000; Vollzeit

Benefits dieser Stelle

Medical and dental coverage

Retirement benefits

Employee stock programs

Relocation assistance

Tuition reimbursement

Discounted products and services

Zusammenfassung

Apple Inc. is seeking a PHY Design Verification Engineer to drive pre-silicon RTL verification of wireless PHY interfaces within a world-class wireless silicon team in California.

You will collaborate with DV methodologists and design teams to create reusable test benches and coverage-driven verification. The role emphasizes ML/AI-assisted debugging, Palladium/FPGA validation, and close alignment with system goals.

Qualifikationen

• Bachelor’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience with ASIC verification flows including test bench development, constrained random testing, and coverage.

Aufgaben

• Review PHY subsystem microarchitecture and create verification plans from specifications.
• Build block/subsystem level test benches with a reference model and reusable architecture.
• Develop and execute directed and constrained random tests, debug failures, and track defects.
• Create and analyze block/subsystem coverage models and add tests to increase coverage.
• Support PHY validation using Palladium and/or FPGA and work to improve DV methodology.

Kenntnisse

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Ausbildung

Bachelor's degree

Tools

Palladium

FPGA

Matlab

C reference model

Jobbeschreibung

Apple Inc. is seeking a PHY Design Verification Engineer to drive pre-silicon RTL verification of wireless PHY interfaces within a world-class wireless silicon team in California.

You will collaborate with DV methodologists and design teams to create reusable test benches and coverage-driven verification. The role emphasizes ML/AI-assisted debugging, Palladium/FPGA validation, and close alignment with system goals.