Wireless SoC DV Engineer: ML-Driven Verification

Apple Inc.; Cupertino (CA); On-site; USD 129,300 - 225,300; Full time

Benefits offered by this job

Medical and dental coverage

Stock programs

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. in the San Francisco Bay Area is seeking a Wireless Design Verification Engineer to join a world-class wireless silicon development team focused on energy-efficient designs and robust verification of MAC/PHY interfaces.

You will build and run pre-silicon testbenches using Verilog/SystemVerilog and UVM, develop coverage, and work across DV methodology with ML/AI techniques. The role includes collaboration with system designers and validation on Palladium/FPGA.

Qualifications

• Bachelor's degree required.
• 3+ years verification experience in wireless/wired blocks.
• Knowledge of Verilog, SystemVerilog, UVM, and SVA.

Responsibilities

• Review MAC subsystem architecture and derive verification plans.
• Build testbenches, create UVM libraries, and maximize reusability.
• Develop and run directed and constrained tests, debug, and track bugs.
• Create block/subsystem coverage models and augment test cases.
• Utilize AI techniques to identify DV issues and improve quality.
• Support MAC validation using Palladium/FPGA.
• Collaborate to enhance DV methodology and flow.

Skills

Verilog/SystemVerilog

UVM

SVA (SystemVerilog Assertions)

Python

Shell scripting

Perl scripting

AI data mining

Palladium/FPGA validation

Bluetooth/WLAN/UWB/Zigbee

Education

Bachelor's degree

Tools

Test bench frameworks

Job description

Apple Inc. in the San Francisco Bay Area is seeking a Wireless Design Verification Engineer to join a world-class wireless silicon development team focused on energy-efficient designs and robust verification of MAC/PHY interfaces.

You will build and run pre-silicon testbenches using Verilog/SystemVerilog and UVM, develop coverage, and work across DV methodology with ML/AI techniques. The role includes collaboration with system designers and validation on Palladium/FPGA.