Senior Wireless PHY Verification Engineer - Multi-Gig WiFi

Apple Inc.

Sunnyvale (CA)

Hybrid

USD 185,000 - 325,000

Full time

13 hours ago
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Job summary

Apple Inc. in Sunnyvale, CA, is seeking a Wireless PHY Design Verification Engineer to join the Wireless Connectivity team.

You will verify WiFi PHY digital systems, architect verification strategies, and enable high-throughput, low-power wireless performance across Apple's products. You will develop UVM environments, testbenches, BFMs, and constrained random scenarios for IEEE 802.11 protocols, driving coverage closure and first-time-right silicon.

Qualifications

  • BS degree in Electrical Engineering or related field.
  • Minimum 10 years of relevant industry experience.
  • Proven track record of multiple tapeouts.
  • Experience verifying wireless, DSP, or digital communication systems.
  • Strong SystemVerilog/UVM testbench expertise.
  • Knowledge of ASIC verification flows and coverage-driven methods.

Responsibilities

  • Develop UVM environments and BFMs for DSP subsystems and IEEE 802.11.
  • Own subsystem verification from test planning to feature closure.
  • Create constrained random scenarios and assertion-based checks.
  • Drive coverage closure with cross-functional teams.
  • Analyze verification data to improve silicon quality.
  • Collaborate across Systems and Design teams to ensure first-time-right silicon.

Skills

SystemVerilog
UVM
Constrained Random
Coverage-driven verification
Debugging simulations
DSP/IEEE 802.11 knowledge
ASIC verification workflow

Education

Bachelor's degree in Electrical Engineering

Job description

Apple Inc. in Sunnyvale, CA, is seeking a Wireless PHY Design Verification Engineer to join the Wireless Connectivity team.

You will verify WiFi PHY digital systems, architect verification strategies, and enable high-throughput, low-power wireless performance across Apple's products. You will develop UVM environments, testbenches, BFMs, and constrained random scenarios for IEEE 802.11 protocols, driving coverage closure and first-time-right silicon.

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