Wireless PHY DV Engineer — Innovative SoC Verification

Apple Inc.; United States; On-site; USD 123,000 - 214,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Discounted products and services

Education reimbursement

Job summary

Apple Inc. is seeking a PHY Design Verification Engineer to drive pre-silicon RTL verification of wireless PHY and interfaces within an energy-efficient wireless SoC.

You will collaborate with DV methodologists, designers, and systems engineers to develop reusable testbenches and coverage-driven verification across the PHY subsystem. You will use advanced DV methodologies, including constrained random testing, metric-driven verification, and AI-assisted debugging, with validation on

Qualifications

• Bachelor's degree in a relevant field.
• MS EE with 2+ years of verification experience preferred.
• Strong knowledge of Verilog/SystemVerilog/UVM and SystemVerilog Assertions.
• Experience in ASIC verification flows and test bench development.
• Familiarity with Matlab and C references, and scripting (Python, Shell, Perl).
• Knowledge of Bluetooth, WLAN, or Zigbee wireless protocols is a plus.

Responsibilities

• Review PHY subsystem microarchitecture and create verification plans.
• Build block/subsystem level test benches with a reference model.
• Develop and execute directed and constrained random tests; debug; drive bug closure.
• Create and analyze coverage models; add tests to improve coverage.
• Apply AI methods to identify DV issues and improve DV quality.
• Support PHY validation using Palladium and/or FPGA.
• Collaborate to improve DV methodology and flow.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

ASIC verification

Python scripting

Shell scripting

Perl scripting

Matlab

AI techniques

FPGA validation

Wireless protocols

Test bench development

Education

Bachelor's degree

MS EE

Tools

Palladium

FPGA

Job description

Apple Inc. is seeking a PHY Design Verification Engineer to drive pre-silicon RTL verification of wireless PHY and interfaces within an energy-efficient wireless SoC.

You will collaborate with DV methodologists, designers, and systems engineers to develop reusable testbenches and coverage-driven verification across the PHY subsystem. You will use advanced DV methodologies, including constrained random testing, metric-driven verification, and AI-assisted debugging, with validation on