Wireless Mixed-Signal Verification Engineer

Apple Inc.; California; Presencial; USD 123.000 - 214.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Employee stock programs

Education reimbursement

Medical and dental coverage

Retirement benefits

Relocation assistance

Descripción de la vacante

Apple Inc. is seeking a Mixed Signal Design Verification Engineer to verify RF and mixed-signal blocks within a wireless SoC. You will interact with analog/RF, digital DV, and wireless system teams to develop verification methodologies that balance coverage and time-to-tapeout.

The role emphasizes building robust testbenches, using SystemVerilog/UVM, and leveraging AI to improve methodologies while collaborating across a world-class engineering team.

Formación

• Bachelor's degree required.
• Experience verifying RF/Mixed-Signal blocks and SOCs.
• Expertise building mixed-signal testbenches and tests using SystemVerilog.
• Experience with UVM methodology and HDL for verification.
• Strong verification, problem solving, testing, and debugging skills.
• Understanding of analog/RF blocks.

Responsabilidades

• Review specifications, extract features, define and execute verification plan.
• Develop top/block level Mixed Signal and Digital testbenches in a UVM framework.
• Build monitors and checkers for RF/Mixed-Signal blocks.
• Debug failures, fix testbench/model issues, manage bug tracking, analyze coverage.
• Write scripts for automation of flow.
• Improve verification methodologies, including AI-driven approaches.

Conocimientos

SystemVerilog

UVM

Verilog HDL

Python

Matlab

Debugging

Educación

Bachelor's degree

Herramientas

Virtuoso Composer

ADE

HED

UPF

Descripción del empleo

Apple Inc. is seeking a Mixed Signal Design Verification Engineer to verify RF and mixed-signal blocks within a wireless SoC. You will interact with analog/RF, digital DV, and wireless system teams to develop verification methodologies that balance coverage and time-to-tapeout.

The role emphasizes building robust testbenches, using SystemVerilog/UVM, and leveraging AI to improve methodologies while collaborating across a world-class engineering team.