Senior Wireless DV Engineer — SoC Verification

Apple Inc.; Waltham (MA); On-site; USD 184,700 - 324,800; Full time

Benefits offered by this job

Medical coverage

Stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Silicon Valley is seeking a Wireless Design Verification Engineer to join its wireless SoC team.

You will drive pre-silicon verification for MAC interfaces, build reusable UVM test benches, and apply AI-assisted DV methods to ensure high-quality silicon. The role collaborates with system and design teams, supports Palladium/FPGA validation, and contributes to coverage-driven verification in a fast-paced environment.

Qualifications

• BS degree and 10+ years of relevant industry experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience with ASIC verification flows, test bench development and coverage.
• Verification experience of MAC/PHY/DMA blocks and wireless protocols.
• Proficiency in Python and shell scripting.

Responsibilities

• Review MAC subsystem microarchitecture and derive verification plans.
• Build and maintain block/subsystem test benches and UVM libraries.
• Develop directed and constrained random tests, debug and close issues.
• Create/extend coverage models and add test cases to raise coverage.
• Apply machine learning/AI to identify DV issues and improve quality.
• Support MAC validation using Palladium and FPGA validation.
• Collaborate with teammates to improve DV methodologies.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Python scripting

Shell scripting

AI-driven DV techniques

Education

BS degree in Electrical Engineering or Computer Science

Tools

Palladium

FPGA

Job description

Apple Inc. in Silicon Valley is seeking a Wireless Design Verification Engineer to join its wireless SoC team.

You will drive pre-silicon verification for MAC interfaces, build reusable UVM test benches, and apply AI-assisted DV methods to ensure high-quality silicon. The role collaborates with system and design teams, supports Palladium/FPGA validation, and contributes to coverage-driven verification in a fast-paced environment.