Wireless SoC Verification Engineer — AI-Driven Testing

Apple Inc.; Irvine (CA); Presencial; USD 130.000 - 170.000; Jornada completa

Descripción de la vacante

Apple Inc. is seeking a Wireless SOC Design Verification Engineer to join its growing wireless silicon team in Irvine, CA.

You will own pre-silicon RTL verification across block, subsystem, and top-level SOC, collaborating with architects, designers, and firmware engineers to build reusable testbenches and verification environments using modern, metric-driven methodology. Responsibilities include writing directed and constrained-random tests, developing coverage models, debugging failures, and

Formación

• Minimum requirement of a bachelor’s degree.
• Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
• Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
• Solid problem-solving and debugging skills with constrained-random verification.
• Understanding of digital logic design, SOC architecture, and microarchitecture.

Responsabilidades

• Partner with architects and designers early to build detailed verification plans from specifications — before RTL lands, not after.
• Develop reusable block/IP and subsystem-level UVM testbenches, and support IP integration into the SOC.
• Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
• Debug failures, including corner cases, and manage bug tracking through resolution.
• Verify low-power design intent using UPF within your scope.
• Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC integration.
• Apply formal verification where it fits — the team will help you ramp up.
• Build and improve automated regression flows and contribute to methodology in your area.
• Explore and apply AI-assisted verification techniques to improve team productivity.
• Participate in verification reviews and uphold high coding-quality standards.
• Support post-silicon bring-up as needed.

Conocimientos

SystemVerilog

Verilog

UVM

Constrained-random testing

Coverage modeling

UPF (low-power verification)

Formal verification

C/C++ programming

Educación

Bachelor's degree in Electrical Engineering or related field

Herramientas

JasperGold

Descripción del empleo

Apple Inc. is seeking a Wireless SOC Design Verification Engineer to join its growing wireless silicon team in Irvine, CA.

You will own pre-silicon RTL verification across block, subsystem, and top-level SOC, collaborating with architects, designers, and firmware engineers to build reusable testbenches and verification environments using modern, metric-driven methodology. Responsibilities include writing directed and constrained-random tests, developing coverage models, debugging failures, and