Wireless SoC DV Engineer RTL/UVM & AI-Driven Testing

Apple Inc.; San Francisco (CA); On-site; USD 129,000 - 225,000; Full time

Job summary

Apple Inc. in the San Francisco Bay Area is seeking a Wireless Design Verification Engineer to drive pre-silicon RTL verification of wireless MAC interfaces within a world-class SoC team.

You will develop reusable testbenches, execute directed and constrained random tests, debug issues, and collaborate across DV teams to elevate verification quality. Familiarity with Verilog/SystemVerilog, UVM, and AI-assisted DV is valued.

Qualifications

• Minimum requirement of a bachelor's degree.
• 3+ years of verification experience of wireless/wired communication block/subsystem.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Verification experience of MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.
• Verification experience of wireless/wired communication block/subsystem.
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
• Proficient in shell and Python scripting, Perl scripting.
• Experience of using AI technologies in data mining/analysis.
• Experience of Palladium/FPGA validation.
• Should be a team player with excellent communication skills, self-motivated and well organized.

Responsibilities

• Review MAC subsystem and create verification plan from specification, review and refine to achieve coverage targets.
• Build block/subsystem level testbenches, create UVM libraries, using the best-in-class DV methodology.
• Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and drive issue closure.
• Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
• Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
• Support MAC subsystem validation using Palladium and/or FPGA.
• Work with team members to improve DV methodology and flow.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Constrained random

Test benches

MAC/PHY/DMA

Wireless protocols

Shell scripting

Python

AI data mining

Palladium/FPGA

Teamwork

Education

Bachelor's degree

Job description

Apple Inc. in the San Francisco Bay Area is seeking a Wireless Design Verification Engineer to drive pre-silicon RTL verification of wireless MAC interfaces within a world-class SoC team.

You will develop reusable testbenches, execute directed and constrained random tests, debug issues, and collaborate across DV teams to elevate verification quality. Familiarity with Verilog/SystemVerilog, UVM, and AI-assisted DV is valued.