Wireless PHY DV Engineer – Pre-Silicon RTL

Apple Inc.; San Francisco (CA); On-site; USD 129,000 - 225,000; Full time

Job summary

Apple in the San Francisco Bay Area seeks a PHY Design Verification Engineer to join a wireless silicon team responsible for energy-efficient SoCs and integration with RF/Analog blocks.

You will build reusable test benches, develop directed and constrained random tests, analyze coverage, and use AI techniques to identify DV issues, with Palladium/FPGA validation support and close collaboration with design teams.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 2+ years of wireless/wired verification experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience with ASIC verification flows including test bench development, constrained random testing, and coverage.
• Proficiency in Matlab and Python.
• Experience with Palladium/FPGA validation.
• Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee.

Responsibilities

• Review PHY subsystem microarchitecture and create verification plans.
• Build test benches with reusable architecture.
• Develop directed and constrained random tests, debug and track bugs.
• Create and analyze coverage models and add test cases to improve coverage.
• Apply AI techniques to identify DV issues and improve quality.
• Support PHY validation using Palladium and/or FPGA.
• Collaborate with team to improve DV methodology and flow.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Matlab

Python

Shell scripting

Perl scripting

AI data mining

Palladium

FPGA validation

Wireless protocols

Team player

Education

Bachelor's degree

MSEE

Tools

Matlab

Python

Job description

Apple in the San Francisco Bay Area seeks a PHY Design Verification Engineer to join a wireless silicon team responsible for energy-efficient SoCs and integration with RF/Analog blocks.

You will build reusable test benches, develop directed and constrained random tests, analyze coverage, and use AI techniques to identify DV issues, with Palladium/FPGA validation support and close collaboration with design teams.