Senior PHY DV Engineer – Wireless SoC & Equity

Apple Inc.; Waltham (MA); On-site; USD 184,700 - 324,800; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Discounted Apple products

Educational assistance

Relocation assistance

Job summary

Apple Inc. in the San Francisco Bay Area seeks a senior PHY Design Verification Engineer to drive pre-silicon RTL verification for wireless PHY and interfaces within a leading SoC.

You will collaborate with DV methodologists, designers, and systems engineers to build reusable test benches and metric-driven verification across RF/Analog arch, Systems/PHY/MAC, and FW/SW integration. This role emphasizes energy-efficient design, AI-assisted verification, and Palladium/FPGA validation, with

Qualifications

• BS and a minimum of 10 years relevant industry experience.

Responsibilities

• Review PHY subsystem microarchitecture and create verification plans from specifications.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertion

ASIC verification

Matlab

Python scripting

Shell scripting

Perl scripting

AI data mining/analysis

Palladium/FPGA validation

Wireless protocols (Bluetooth/UWB/WLAN

Education

Bachelor's degree

Tools

Palladium

Job description

Apple Inc. in the San Francisco Bay Area seeks a senior PHY Design Verification Engineer to drive pre-silicon RTL verification for wireless PHY and interfaces within a leading SoC.

You will collaborate with DV methodologists, designers, and systems engineers to build reusable test benches and metric-driven verification across RF/Analog arch, Systems/PHY/MAC, and FW/SW integration. This role emphasizes energy-efficient design, AI-assisted verification, and Palladium/FPGA validation, with