PHY Design Verification Engineer

Apple Inc.; Cupertino (CA); On-site; USD 129,300 - 225,300; Full time

Job summary

Apple seeks a PHY Design Verification Engineer in the San Francisco Bay Area to contribute to wireless silicon development and DV methodology. You will build and run constrained-random tests, develop test benches, and verify pre-silicon RTL for wireless PHY interfaces, collaborating with RF/Analog, Systems, and FW teams.

Preferred skills include Verilog/SystemVerilog/UVM, Matlab, and FPGA validation, with a background in ASIC verification flows and test coverage.

Qualifications

• Bachelor's degree in a relevant field; MSEE preferred.
• 2+ years in verification of wireless/wired blocks or subsystems.
• Strong Verilog/SystemVerilog, UVM, and assertion knowledge.
• Experience with ASIC verification flows and test benches.

Responsibilities

• Review PHY subsystem specs and craft verification plans to target coverage.
• Build reusable block/subsystem test benches with reference models.
• Develop directed and constrained random tests, debug and close issues.
• Create and analyze coverage models; expand test cases to raise coverage.
• Utilize AI/ML to identify DV issues and improve quality.
• Support PHY validation using Palladium/FPGA; collaborate with teams.

Skills

Verilog

SystemVerilog

UVM

Python

Shell scripting

Education

Bachelor's degree

MSEE

Tools

Palladium

FPGA

Matlab

Job description

San Francisco Bay Area, California, United States Hardware

Would you like to join Apple’s growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering.

Description

In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.

Responsibilities

• Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets.
• Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
• Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
• Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
• Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
• Support PHY subsystem validation using Palladium and/or FPGA.
• Work with team members to improve DV methodology and flow.

Minimum Qualifications

• Minimum requirement of a bachelors degree

Preferred Qualifications

• MSEE with 2+ years of verification experience of wireless/wired communication block/subsystem.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Experience of using Matlab/C reference model and bit-accurate verification.
• Verification experience of wireless/wired communication block/subsystem.
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
• Proficient in shell and Python scripting, Perl scripting.
• Experience of using AI technologies in data mining/analysis.
• Experience of Palladium/FPGA validation.
• Should be a team player with excellent communication skills, self-motivated and well organized.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $225,300, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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