Wireless PHY Verification Engineer | RTL, DV & AI-Driven Testing

Apple Inc.; San Diego (CA); On-site; USD 122,700 - 214,300; Full time

Benefits offered by this job

Apple Benefits

Stock programs

Relocation assistance

Education reimbursement

Job summary

Apple Inc. in San Diego, CA, seeks a dedicated PHY Design Verification Engineer to drive pre-silicon RTL verification for wireless PHY and its interfaces within a world-class SoC team.

You will develop reusable testbenches, plan verification, run directed and constrained tests, and collaborate with RF/Analog, Systems, and FW/SW engineering to improve DV quality. The role emphasizes ML/AI-driven defect detection, coverage analysis, and validation on Palladium/FPGA, with opportunities to influence

Qualifications

• Bachelor's degree is the minimum requirement.
• MSEE with 2+ years of verification experience preferred.
• Advanced knowledge of Verilog, SystemVerilog, UVM and SVAs.
• Experience with ASIC verification flows including test bench development.
• Experience using Matlab/C reference models and bit-accurate verification.
• Knowledge of wireless protocols such as Bluetooth, WLAN, Zigbee.
• Proficient in shell and Python scripting; Perl scripting helpful.
• Experience with AI/data mining for verification is a plus.
• Strong communication, teamwork, and organization.

Responsibilities

• Review PHY subsystem microarchitecture and create verification plans.
• Build reusable test benches with a reference model and DV methodology.
• Develop and execute directed and constrained random tests; debug and track bugs.
• Create and analyze block/subsystem coverage models and add test cases.
• Use ML/AI to identify issues and improve DV quality.
• Support PHY validation using Palladium and FPGA; drive issue closure.
• Collaborate with team to improve DV workflow and methodology.

Education

Bachelor's degree

Master of Science in Electrical Engineering (MSEE)

Tools

Verilog

SystemVerilog

UVM

SystemVerilog Assertion

Matlab

Python scripting

Shell scripting

Perl scripting

Palladium/FPGA validation

Job description

Apple Inc. in San Diego, CA, seeks a dedicated PHY Design Verification Engineer to drive pre-silicon RTL verification for wireless PHY and its interfaces within a world-class SoC team.

You will develop reusable testbenches, plan verification, run directed and constrained tests, and collaborate with RF/Analog, Systems, and FW/SW engineering to improve DV quality. The role emphasizes ML/AI-driven defect detection, coverage analysis, and validation on Palladium/FPGA, with opportunities to influence