PHY Design Verification Engineer

Apple Inc.; Waltham (MA); On-site; USD 184,700 - 324,800; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Discounted Apple products

Educational assistance

Relocation assistance

Job summary

Apple Inc. in the San Francisco Bay Area seeks a senior PHY Design Verification Engineer to drive pre-silicon RTL verification for wireless PHY and interfaces within a leading SoC.

You will collaborate with DV methodologists, designers, and systems engineers to build reusable test benches and metric-driven verification across RF/Analog arch, Systems/PHY/MAC, and FW/SW integration. This role emphasizes energy-efficient design, AI-assisted verification, and Palladium/FPGA validation, with

Qualifications

• BS and a minimum of 10 years relevant industry experience.

Responsibilities

• Review PHY subsystem microarchitecture and create verification plans from specifications.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertion

ASIC verification

Matlab

Python scripting

Shell scripting

Perl scripting

AI data mining/analysis

Palladium/FPGA validation

Wireless protocols (Bluetooth/UWB/WLAN

Education

Bachelor's degree

Tools

Palladium

Job description

San Francisco Bay Area, California, United States Hardware

Would you like to join Apple’s growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy‑efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world‑class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering.

Description

In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world‑class silicon to empower wireless products for hundreds of millions of customers. As a PHY Design Verification Engineer, you will be responsible for pre‑silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric‑driven verification, ensuring the highest design quality.

Responsibilities

• Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets.
• Build block/subsystem level test benches with a reference model, using the best‑in‑class DV methodology. Architect test benches with maximum reusability in mind.
• Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
• Create and analyze block/subsystem‑level coverage models, and add test cases to increase coverage.
• Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
• Support PHY subsystem validation using Palladium and/or FPGA.
• Work with team members to improve DV methodology and flow.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience

Preferred Qualifications

• Verification experience of wireless/wired communication block/subsystem.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Experience of using Matlab/C reference model and bit‑accurate verification.
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
• Proficient in shell and Python scripting, Perl scripting.
• Experience of using AI technologies in data mining/analysis.
• Experience of Palladium/FPGA validation.
• Should be a team player with excellent communication skills, self‑motivated and well organized.

At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

You’ll also receive benefits including:

• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing your career at Apple
• Possible discretionary bonuses or commission payments as well as relocation assistance

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Apple accepts applications to this posting on an ongoing basis.