Wireless PHY Verification Engineer – RTL/UVM Specialist

Apple Inc.; Cupertino (CA); On-site; USD 129,300 - 225,300; Full time

Job summary

Apple seeks a PHY Design Verification Engineer in the San Francisco Bay Area to contribute to wireless silicon development and DV methodology. You will build and run constrained-random tests, develop test benches, and verify pre-silicon RTL for wireless PHY interfaces, collaborating with RF/Analog, Systems, and FW teams.

Preferred skills include Verilog/SystemVerilog/UVM, Matlab, and FPGA validation, with a background in ASIC verification flows and test coverage.

Qualifications

• Bachelor's degree in a relevant field; MSEE preferred.
• 2+ years in verification of wireless/wired blocks or subsystems.
• Strong Verilog/SystemVerilog, UVM, and assertion knowledge.
• Experience with ASIC verification flows and test benches.

Responsibilities

• Review PHY subsystem specs and craft verification plans to target coverage.
• Build reusable block/subsystem test benches with reference models.
• Develop directed and constrained random tests, debug and close issues.
• Create and analyze coverage models; expand test cases to raise coverage.
• Utilize AI/ML to identify DV issues and improve quality.
• Support PHY validation using Palladium/FPGA; collaborate with teams.

Skills

Verilog

SystemVerilog

UVM

Python

Shell scripting

Education

Bachelor's degree

MSEE

Tools

Palladium

FPGA

Matlab

Job description

Apple seeks a PHY Design Verification Engineer in the San Francisco Bay Area to contribute to wireless silicon development and DV methodology. You will build and run constrained-random tests, develop test benches, and verify pre-silicon RTL for wireless PHY interfaces, collaborating with RF/Analog, Systems, and FW teams.

Preferred skills include Verilog/SystemVerilog/UVM, Matlab, and FPGA validation, with a background in ASIC verification flows and test coverage.