Video Codec ASIC Engineer

ByteDance; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k) with company match

Paid parental leave

Disability insurance

Life insurance

Wellbeing benefits

10 holidays per year

10 sick days per year

Paid personal time

Job summary

ByteDance seeks an ASIC Design Engineer for the Video Silicon IP team to build high-performance video codec hardware (FPGA/ASIC) from the ground up and work with architecture, algorithm, software, firmware, and verification experts.

You will design RTL for codec pipelines, optimize area/power/performance, and ensure functional correctness with the verification team using UVM test benches, while coordinating with synthesis and floor planning for timing closure.

Qualifications

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, AXI/APB, SV assertions.
• Python for EDA flow automation.

Responsibilities

• Design RTL for video codec pipeline stages including intra/inter prediction, transform, and entropy coding.
• Drive functional correctness with verification teams using UVM test benches and debug RTL coverage.
• Understand synthesis, timing analysis, and CDC/RDC checks; collaborate with floor planning and timing closure.

Skills

ASIC front-end design

SystemVerilog

UVM

C++

Python

VLSI concepts

Scripting for EDA

Education

MS/PhD in Electrical Engineering or related field

Tools

SystemVerilog RTL

HDL

HLS

Job description

ByteDance seeks an ASIC Design Engineer for the Video Silicon IP team to build high-performance video codec hardware (FPGA/ASIC) from the ground up and work with architecture, algorithm, software, firmware, and verification experts.

You will design RTL for codec pipelines, optimize area/power/performance, and ensure functional correctness with the verification team using UVM test benches, while coordinating with synthesis and floor planning for timing closure.