Video Codec ASIC Engineer (Graduate)

Pangle; San Jose (CA); Hybrid; USD 128,000 - 317,000; Full time

Job summary

ByteDance in San Jose is seeking an ASIC Design Engineer Graduate (Video Silicon IP) for a 2027 start. You will join the Technology team to design hardware accelerators for video encoding and processing on FPGA/ASIC, working with experts across algorithm, architecture, software, firmware and verification.

As a graduate, you will explore bold ideas, tackle challenging problems, and grow quickly. Applicants should be finishing a Master's in CS or EE, with knowledge of video codecs and RTL

Qualifications

• Master's degree in CS, EE, or a related field.
• Knowledge of video codecs.
• Experience with RTL design (SystemVerilog) or High Level Synthesis (HLS).
• Experience with UVM, SystemC, or DPI.
• Good programming skills in Python for task automation.

Skills

Video codecs

SystemVerilog RTL

High level Synthesis (HLS)

UVM

SystemC/DPI

Python

Education

Master's degree in CS/EE

Tools

SystemVerilog

HLS tools

Job description

ByteDance in San Jose is seeking an ASIC Design Engineer Graduate (Video Silicon IP) for a 2027 start. You will join the Technology team to design hardware accelerators for video encoding and processing on FPGA/ASIC, working with experts across algorithm, architecture, software, firmware and verification.

As a graduate, you will explore bold ideas, tackle challenging problems, and grow quickly. Applicants should be finishing a Master's in CS or EE, with knowledge of video codecs and RTL