Video Silicon IP ASIC Design Intern — Hands-on

Bytedance; San Jose (CA); On-site; USD 28,000 - 41,000; Full time

Job summary

ByteDance’s internship program offers hands-on experience in video codec hardware development, working on ASIC/FPGA projects within a fast-growing team. You will gain practical exposure to real-world challenges and participate in development workshops alongside industry professionals.

As an ASIC Design Engineer intern, you will collaborate with architecture, algorithm and verification teams to build high-performance video processing IPs and apply RTL/SystemVerilog and Python for automation

Qualifications

• Currently pursuing a Master's in computer science/electrical engineering or a related technical discipline
• Knowledge of Video Codecs
• Experience with RTL design (SystemVerilog) or High level Synthesis (HLS)
• Experience with UVM methodology, SystemC, or DPI
• Good programming skills in Python for task automation

Responsibilities

• Collaborate with architecture, algorithm and verification teams to build high-performance video processing IPs for ASIC design
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos

Skills

Video Codecs

RTL design

SystemVerilog

UVM

Python

Education

Master's in computer science or electrical engineering

Job description

ByteDance’s internship program offers hands-on experience in video codec hardware development, working on ASIC/FPGA projects within a fast-growing team. You will gain practical exposure to real-world challenges and participate in development workshops alongside industry professionals.

As an ASIC Design Engineer intern, you will collaborate with architecture, algorithm and verification teams to build high-performance video processing IPs and apply RTL/SystemVerilog and Python for automation