SoC Video Codec RTL Engineer (FPGA/ASIC)

TikTok; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Job summary

TikTok is seeking a video codec hardware design engineer in San Jose to help build industry-leading FPGA/ASIC accelerators for advanced video encoding and processing. You will join a fast-growing team of architects, verification, and software/hardware engineers delivering large-scale video platforms and services.

Responsibilities include architecture design for SoC subsystems, RTL implementation in Verilog/SystemVerilog, front-end quality checks, cross-functional collaboration for synthesis and

Qualifications

• Bachelor’s degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
• 1+ years of experience in digital front-end design or strong potential.
• Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
• Proficiency with mainstream front-end EDA tools (Spyglass, Design Compiler, PrimeTime).
• Fluent in scripting languages (Python, Perl, Tcl, Makefile) for workflow automation.

Responsibilities

• Architecture Design: Define architecture of SoC top or subsystems; evaluate Power, Performance, and Area (PPA).
• RTL Implementation: Write high-quality RTL code (Verilog/SystemVerilog) and maintain docs.
• Front-End Quality Control: Perform Lint, CDC, and RDC checks for design robustness.
• Cross-Functional Collaboration: Work with Verification and Backend/Mid-end teams for synthesis, SDC, STA, and power optimization.
• Low Power Design: Develop chip low-power strategies, apply Clock Gating and Power Gating, UPF flow.

Skills

Verilog/SystemVerilog

Python/Perl/Tcl scripting

Digital front-end design

Education

Bachelor’s degree or higher in Microelectronics/ICs/EE/CS

Tools

Spyglass

Design Compiler

PrimeTime

Job description

TikTok is seeking a video codec hardware design engineer in San Jose to help build industry-leading FPGA/ASIC accelerators for advanced video encoding and processing. You will join a fast-growing team of architects, verification, and software/hardware engineers delivering large-scale video platforms and services.

Responsibilities include architecture design for SoC subsystems, RTL implementation in Verilog/SystemVerilog, front-end quality checks, cross-functional collaboration for synthesis and