Video ASIC Design Engineer: High-Performance Codec IP

Bytedance; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

ByteDance is hiring ASIC design engineers to build high-performance video codec hardware IP (FPGA/ASIC) in the Video Silicon IP team in San Jose. You will work with architecture, algorithm, software, and hardware teams to meet tight PPA targets and deliver scalable video processing hardware.

The role emphasizes collaboration across RTL design, verification, synthesis, and physical design, as well as Python scripting for automation and exposure to modern video codecs.

Qualifications

• M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, AXI/APB, SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.
• Preferred: Video Codec experience (H.265/HEVC, H.266/VVC, AV1, VP9, H.264/AVC).
• Preferred: ISP or ML based image/video compression experience.
• Preferred: FPGA prototyping for pre-silicon codec validation and using LLMs to assist RTL workflows.

Responsibilities

• Design RTL for video codec pipeline stages including intra/inter prediction, transform, entropy coding, and in-loop filters.
• Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec specifications into hardware architectures.
• Drive functional correctness with verification using directed and constrained-random UVM test benches.
• Coordinate with synthesis, timing analysis, and floorplanning with physical design teams.

Skills

SystemVerilog RTL design

HLS

UVM/DPI/C++

Python scripting

VLSI design concepts

ASIC frontend design

Education

M.S./Ph.D. in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog tools

UVM test benches

Job description

ByteDance is hiring ASIC design engineers to build high-performance video codec hardware IP (FPGA/ASIC) in the Video Silicon IP team in San Jose. You will work with architecture, algorithm, software, and hardware teams to meet tight PPA targets and deliver scalable video processing hardware.

The role emphasizes collaboration across RTL design, verification, synthesis, and physical design, as well as Python scripting for automation and exposure to modern video codecs.