Video Codec ASIC Design Intern – High-Performance IP

ByteDance; San Jose (CA); On-site; USD 51,000 - 73,000; Full time

Job summary

ByteDance in the San Jose area is seeking an ASIC Design Intern for our Video Silicon IP team. You will work with architecture, algorithm and verification groups to design high‑performance, low‑power video processing IPs and accelerators for advanced encoding and processing.

This internship offers hands-on experience, exposure to real-world challenges, and development workshops. Please include your availability start and end dates in your resume.

Qualifications

• Currently pursuing an Undergraduate in computer science/electrical engineering or a related technical discipline
• Knowledge of Video Codecs
• Experience with RTL design (SystemVerilog) or High level Synthesis (HLS)
• Experience with UVM methodology, SystemC, or DPI
• Good programming skills in Python for task automation

Responsibilities

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos

Skills

Video Codecs

Python

Education

Undergraduate in computer science / electrical engineering

Tools

SystemVerilog

HLS

SystemC

DPI

Job description

ByteDance in the San Jose area is seeking an ASIC Design Intern for our Video Silicon IP team. You will work with architecture, algorithm and verification groups to design high‑performance, low‑power video processing IPs and accelerators for advanced encoding and processing.

This internship offers hands-on experience, exposure to real-world challenges, and development workshops. Please include your availability start and end dates in your resume.