ASIC Design Engineer (Video Silicon IP) - Multimedia Lab San Jose Regular

Bytedance; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

ByteDance is hiring ASIC design engineers to build high-performance video codec hardware IP (FPGA/ASIC) in the Video Silicon IP team in San Jose. You will work with architecture, algorithm, software, and hardware teams to meet tight PPA targets and deliver scalable video processing hardware.

The role emphasizes collaboration across RTL design, verification, synthesis, and physical design, as well as Python scripting for automation and exposure to modern video codecs.

Qualifications

• M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, AXI/APB, SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.
• Preferred: Video Codec experience (H.265/HEVC, H.266/VVC, AV1, VP9, H.264/AVC).
• Preferred: ISP or ML based image/video compression experience.
• Preferred: FPGA prototyping for pre-silicon codec validation and using LLMs to assist RTL workflows.

Responsibilities

• Design RTL for video codec pipeline stages including intra/inter prediction, transform, entropy coding, and in-loop filters.
• Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec specifications into hardware architectures.
• Drive functional correctness with verification using directed and constrained-random UVM test benches.
• Coordinate with synthesis, timing analysis, and floorplanning with physical design teams.

Skills

SystemVerilog RTL design

HLS

UVM/DPI/C++

Python scripting

VLSI design concepts

ASIC frontend design

Education

M.S./Ph.D. in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog tools

UVM test benches

Job description

Join us as we work together to inspire creativity and enrich life around the globe.

Location:

San Jose

Team:

Technology

Employment Type:

Regular

Job Code:

A100401

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Responsibilities

Team IntroductionThe Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
• Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec standard specifications and proprietary codec improvements into implementable hardware architectures.
• Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
• Drive functional correctness in partnership with the verification team using directed and constrained-random UVM test benches; debug and close RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; work with physical design on floor plan and timing closure guidance.

Qualifications

• Minimum Qualifications- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum Qualifications- 2 years of ASIC front-end design experience as a primary RTL owner.
• Minimum Qualifications- Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Minimum Qualifications- Familiarity with UVM/DPI/C++.
• Minimum Qualifications- Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Minimum Qualifications- Scripting proficiency in Python for EDA flow automation.
• Preferred Qualifications- Experience with Video Codec (H.265/HEVC, H.266/VVC, AV1, VP9, or H.264/AVC) is a big plus.
• Preferred Qualifications- Experience with relevant ISP or machine learning based image/video compression.
• Preferred Qualifications- Experience with FPGA prototyping for pre-silicon codec validation.
• Preferred Qualifications- Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.

Job Information

About Us

Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.

Why Join ByteDance

Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.

As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.

Diversity & Inclusion

ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.

Reasonable Accommodation

ByteDance is committed to providing reasonable accommodations in our recruitment processes for candidates with disabilities, pregnancy, sincerely held religious beliefs or other reasons protected by applicable laws. If you need assistance or a reasonable accommodation, please reach out to us at https://tinyurl.com/RA-request