Graduate ASIC Design Engineer – Video Codec Hardware

Bytedance; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 230,000; Full time

Job summary

ByteDance is seeking an ASIC Design Engineer to build industry-leading video codec hardware IPs (FPGA/ASIC) for high-performance video processing. You will work with architecture, algorithms, software, firmware, and verification teams on scalable, low-power designs.

The role requires strong RTL design experience, HDL proficiency, and Python scripting. A Bachelor's in CS/EE and knowledge of video codecs are essential. On-site in San Jose with regular employment type.

Qualifications

• Must have a Bachelor's degree in Computer Science, Electrical Engineering or related field.
• Knowledge of video codecs and RTL-based design.
• Experience with UVM, SystemC, or DPI.
• Strong Python programming for automation tasks.

Responsibilities

• Design ASIC video codec IPs for compression and processing of images and video.
• Collaborate with architecture, algorithms, software, firmware, and verification teams to deliver high-performance, low-power solutions.

Skills

Video codecs

RTL SystemVerilog

UVM/SystemC/DPI

Python automation

Education

Bachelor's degree in CS/EE

Job description

ByteDance is seeking an ASIC Design Engineer to build industry-leading video codec hardware IPs (FPGA/ASIC) for high-performance video processing. You will work with architecture, algorithms, software, firmware, and verification teams on scalable, low-power designs.

The role requires strong RTL design experience, HDL proficiency, and Python scripting. A Bachelor's in CS/EE and knowledge of video codecs are essential. On-site in San Jose with regular employment type.