TPU SoC RTL Design Engineer — Equity & Impact

Google LLC; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC is seeking an experienced SoC Design Engineer in Sunnyvale, CA to shape AI/ML hardware acceleration through RTL design and verification for TPUs. You will contribute to clocking, reset, and timing-critical RTL development, collaborating with architecture, power, DV, and physical design teams to deliver high-performance, energy-efficient ASIC solutions.

The role emphasizes cross-functional collaboration and production-grade design for data center accelerators, with a strong focus on

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Responsibilities

• Work independently to create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

RTL design experience

SystemVerilog

Scripting (Python/Tcl/Perl)

Clocking & timing analysis

Education

Bachelor's degree in EE/CE/CS or equivalent

Tools

EDA tools

Job description

Google LLC is seeking an experienced SoC Design Engineer in Sunnyvale, CA to shape AI/ML hardware acceleration through RTL design and verification for TPUs. You will contribute to clocking, reset, and timing-critical RTL development, collaborating with architecture, power, DV, and physical design teams to deliver high-performance, energy-efficient ASIC solutions.

The role emphasizes cross-functional collaboration and production-grade design for data center accelerators, with a strong focus on