TPU PCIe RTL Design Lead — AI Accelerator

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Sunnyvale seeks a PCIe Design Engineer to shape the PCIe/SoC RTL for next-generation data center accelerators. You will architect and implement SoC-level RTL, building core infrastructure like clocking, reset, and chip management, while collaborating with software and hardware teams to deliver high-performance accelerators.

You will contribute to TPUs and AI hardware efforts, verifying complex digital designs with emphasis on TPU architecture integration within AI/ML systems.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Responsibilities

• Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that meet PPA targets and quality guidelines.
• Manage the full RTL lifecycle, including documentation and coding, with sign-off readiness for Lint, CDC, and synthesis.
• Partner with system architects to integrate the PCIe subsystem to meet bandwidth, latency, and power goals.
• Coordinate with Verification and Physical Design teams to develop test plans, use PCIe VIP, and achieve timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up for link integrity and subsystem performance.

Skills

ASIC design

PCIe protocol

RTL debugging

SystemVerilog/Verilog

PCIe LTSSM

CDC/timing closure

Python/Perl scripting

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Verdi/VCS

PCIe VIP

Job description

Google Sunnyvale seeks a PCIe Design Engineer to shape the PCIe/SoC RTL for next-generation data center accelerators. You will architect and implement SoC-level RTL, building core infrastructure like clocking, reset, and chip management, while collaborating with software and hardware teams to deliver high-performance accelerators.

You will contribute to TPUs and AI hardware efforts, verifying complex digital designs with emphasis on TPU architecture integration within AI/ML systems.