TPU RTL Design Engineer for AI Hardware

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Performance bonus

Equity

Benefits

Job summary

Google is seeking a highly skilled RTL/ASIC design engineer in Sunnyvale, CA to help shape AI/ML hardware acceleration with TPUs. You will design RTL IP, verify complex digital blocks, and collaborate with verification and physical design teams to meet timing and power targets.

You will work on inter-chip high-speed interconnect subsystems, contribute to architecture and microarchitecture definitions for the next generation TPU, and help scale AI workloads across Google's data centers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across MAC, L2, or PHY layers.
• Experience with high-speed interconnects.

Responsibilities

• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Define and document the microarchitecture for complex digital designs within the TPU.
• Write high-quality, performant, and power-efficient RTL code, primarily in SystemVerilog.

Skills

ASIC design

RTL design

Networking IP

SystemVerilog

High-speed interconnects

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS

Tools

CDC

RDC

RTL Linting

LEC

Job description

Google is seeking a highly skilled RTL/ASIC design engineer in Sunnyvale, CA to help shape AI/ML hardware acceleration with TPUs. You will design RTL IP, verify complex digital blocks, and collaborate with verification and physical design teams to meet timing and power targets.

You will work on inter-chip high-speed interconnect subsystems, contribute to architecture and microarchitecture definitions for the next generation TPU, and help scale AI workloads across Google's data centers.