RTL Design Engineer for TPU ASIC – AI Hardware

Google LLC

Sunnyvale (CA)

On-site

USD 163,000 - 236,000

Full time

32 hours ago
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Job summary

Google Sunnyvale, CA, is seeking an experienced RTL design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, design RTL IP for ASIC products, and collaborate with software and system hardware teams to bring complex digital designs from concept to production.

The role focuses on SoC RTL design for data center accelerators, clocking and reset management, integration with software, and collaboration across multiple teams to deliver scalable AI solutions.

Qualifications

  • Bachelor's degree or equivalent practical experience required.
  • Experience with scripting languages is required.

Responsibilities

  • Create and review management and control subsystem design microarchitecture specifications.
  • Develop SystemVerilog RTL to implement logic for ASIC products per guidelines.
  • Collaborate with architecture and power teams to evaluate features and impact.
  • Work with design validation teams to create test plans and debug RTL.
  • Coordinate with physical design teams to meet timing and physical requirements.

Skills

Scripting languages

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
Master's or PhD in Electrical Engineering, Computer Engineering or Computer Science (emphasis on computer architecture)

Tools

SystemVerilog

Job description

Google Sunnyvale, CA, is seeking an experienced RTL design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, design RTL IP for ASIC products, and collaborate with software and system hardware teams to bring complex digital designs from concept to production.

The role focuses on SoC RTL design for data center accelerators, clocking and reset management, integration with software, and collaboration across multiple teams to deliver scalable AI solutions.

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