TPU RTL Silicon Design Manager — Lead AI Hardware

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google is recruiting a Silicon Design Manager in Sunnyvale to shape the future of AI/ML hardware acceleration for TPUs. You will drive high-performance, low-power silicon, collaborating with architects, software teams, and cross-functional groups to enable clocking, power management, and architectural feasibility.

You will guide a team of RTL Design Engineers, define timing goals, and ensure physical design closure while pushing innovation in TPU architectures used across Google's AI platforms.

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent practical experience.
• 10 years of experience with chip design, ASIC digital design and SystemVerilog.
• 8 years in computer architecture and RTL.
• 3 years in people management and developing employees.

Responsibilities

• Lead RTL design engineers on IP development for Compute Cores.
• Provide technical leadership, model best design practices and review designs.
• Be primary contact for design activities, architecture estimation and power/performance trade-offs.
• Collaborate with Verification, DFT, Physical Design, and Software teams throughout the cycle.
• Drive improvements in design methodologies and quality controls.

Skills

Chip Design

ASIC Digital Design

SystemVerilog

People management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

DFT

Verification

Synthesis

STA

Physical Design

Job description

Google is recruiting a Silicon Design Manager in Sunnyvale to shape the future of AI/ML hardware acceleration for TPUs. You will drive high-performance, low-power silicon, collaborating with architects, software teams, and cross-functional groups to enable clocking, power management, and architectural feasibility.

You will guide a team of RTL Design Engineers, define timing goals, and ensure physical design closure while pushing innovation in TPU architectures used across Google's AI platforms.