Silicon Design Manager: RTL/ML Accelerator Architect

Minority Professional Network, Inc.; Sunnyvale, Northern (CA, KY); Hybrid; USD 192,000 - 278,000; Full time

Job summary

Google is seeking a Silicon Design Manager to shape the future of AI/ML hardware acceleration and drive TPU architecture and integration. You will lead a team of RTL engineers, mentor performance-focused designers, and collaborate with cross-functional groups to deliver high‑quality TPU IP and compute cores.

You will work with architects to set timing goals, explore physical design trade-offs, and coordinate with software teams on clocking and power management, enabling scalable AI solutions

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent experience.
• 10+ years in chip design, ASIC Digital Design, SystemVerilog.
• 8+ years in Computer Architecture and RTL.
• 3+ years in people management.

Responsibilities

• Lead RTL Design Engineers for IP development on Compute Cores.
• Provide technical leadership, architecture reviews, and design methodologies.
• Primary contact for design activities; coordinate with Architecture and System Design teams.
• Collaborate with Verification, DFT, Physical Design, and Software teams.
• Drive improvements in design processes and quality control.

Skills

Bachelor's degree

Chip Design

ASIC Digital Design

SystemVerilog

People management

Education

Bachelor's degree in EE/CE/CS

Master's degree or PhD preferred

Tools

DFT

STA

Synthesis

Physical Design

Job description

Google is seeking a Silicon Design Manager to shape the future of AI/ML hardware acceleration and drive TPU architecture and integration. You will lead a team of RTL engineers, mentor performance-focused designers, and collaborate with cross-functional groups to deliver high‑quality TPU IP and compute cores.

You will work with architects to set timing goals, explore physical design trade-offs, and coordinate with software teams on clocking and power management, enabling scalable AI solutions