Silicon Design Lead: RTL ML & TPU Accelerators

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target (20%)

Benefits package

Job summary

Google LLC is seeking a Silicon Design Manager to drive RTL machine learning accelerator design, focusing on TPU architecture and integration within AI/ML systems. You will shape high-performance, low-power hardware and lead a team of RTL engineers.

The role collaborates with Architects, Verifications, and Software teams to meet timing, power, and performance goals. Applicants should have a strong background in ASIC design and SystemVerilog, plus senior leadership experience.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and RTL.
• 3 years of experience in people management and developing employees.

Responsibilities

• Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices.
• Serve as the primary point of contact for all design-related activities on projects with Architecture and System Design teams.
• Collaborate with cross-functional teams to plan design, power optimization, and performance improvements.
• Drive improvements in design methodologies, processes, and quality control measures.

Skills

Chip design

ASIC digital design

SystemVerilog

Computer architecture

RTL design

People management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD preferred

Tools

DFT

Synthesis

STA

Physical Design

Job description

Google LLC is seeking a Silicon Design Manager to drive RTL machine learning accelerator design, focusing on TPU architecture and integration within AI/ML systems. You will shape high-performance, low-power hardware and lead a team of RTL engineers.

The role collaborates with Architects, Verifications, and Software teams to meet timing, power, and performance goals. Applicants should have a strong background in ASIC design and SystemVerilog, plus senior leadership experience.