AI/ML Hardware Design Lead for TPU Innovation

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus

Job summary

Google LLC in Sunnyvale, CA is seeking a senior hardware designer to shape the future of AI/ML hardware acceleration. You’ll own critical datapath blocks, drive RTL-to-GDSII flow including synthesis, floorplanning, PNR, timing closure and signoff for TPUs and related accelerators.

The role requires a track record in physical design, sub-7nm processes and high-density macros, plus leadership of a small team and scripting for layout automation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design, including custom structured datapath implementation.
• Experience hardening dense compute units into high-frequency, low-power macros.
• Experience in sub-7nm process nodes, managing the physical density and routing congestion typical of custom datapaths.

Responsibilities

• Own critical datapath and matrix multiplication accumulator blocks, driving RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
• Understand math-intensive micro-architecture to perform feasibility studies, analyzing performance, power, and area tradeoffs for design closure.
• Develop and improve advanced physical design methodologies and customize implementation recipes, managing different PNR tools (Synopsys Fusion Compiler, Cadence Innovus/Genus, PrimeTime, StarRC, Calibre, Apache Redhawk).
• Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis, timing closure, routing, extraction, physical verification (DRC/LVS, EM/IR), and final signoff.
• Lead sub-chip execution and mentor a small team of engineers to ensure on-schedule delivery.

Skills

Datapath design

RTL-to-GDSII

Physical design

Sub-7nm

EDA scripting

Leadership

Education

Bachelor's degree in EE/CE/CS

Master's or PhD preferred

Tools

Synopsys Fusion Compiler

Cadence Innovus

Cadence Genus

PrimeTime

StarRC

Calibre

Apache Redhawk

Job description

Google LLC in Sunnyvale, CA is seeking a senior hardware designer to shape the future of AI/ML hardware acceleration. You’ll own critical datapath blocks, drive RTL-to-GDSII flow including synthesis, floorplanning, PNR, timing closure and signoff for TPUs and related accelerators.

The role requires a track record in physical design, sub-7nm processes and high-density macros, plus leadership of a small team and scripting for layout automation.