Senior Physical Design Lead — AI Silicon, TPUs & Equity

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking a senior hardware design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, verify complex digital designs, and oversee RTL-to-GDSII flows including synthesis, floorplanning, place and route (PNR), timing closure, and physical signoff.

You will mentor a small team and collaborate across Google''s AI/ML hardware initiatives. The role focuses on performance, power, and area tradeoffs in sub-7nm processes, influencing product pipelines

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design, including custom structured datapath implementation.
• Experience hardening dense compute units (e.g., dot-product engines, MACs, multipliers, ALUs) into high-frequency, low-power macros.
• Experience in sub-7nm process nodes (FinFET and Gate-All-Around) managing density and routing in custom datapaths.

Responsibilities

• Own critical custom datapath and matrix multiplication accumulator blocks, driving RTL-to-GDSII including synthesis, floor-planning, PNR, timing closure, and physical sign-off.
• Perform detailed feasibility studies, analyzing performance, power, and area tradeoffs to achieve design closure.
• Develop and improve advanced physical design methodologies and customize implementation recipes; manage PNR tools (Synopsys Fusion Compiler, Cadence Innovus/Genus, PrimeTime, StarRC, Calibre, Apache Redhawk).
• Execute steps: floor-planning, synthesis, placement, CTS, timing closure, routing, extraction, physical verification (DRC/LVS), EM/IR, final signoff.
• Lead sub-chip execution and mentor a small team to ensure on-schedule project completion.

Skills

Physical design experience

Sub-7nm process knowledge

High-frequency low-power macros

Datapath implementation

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synthesis tools

Place-and-route tools

Timing analysis tools

Layout verification tools

Circuit/logic simulation tools

Job description

Google is seeking a senior hardware design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, verify complex digital designs, and oversee RTL-to-GDSII flows including synthesis, floorplanning, place and route (PNR), timing closure, and physical signoff.

You will mentor a small team and collaborate across Google''s AI/ML hardware initiatives. The role focuses on performance, power, and area tradeoffs in sub-7nm processes, influencing product pipelines