TPU ASIC Physical Design Lead – High-Impact AI Silicon

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking a skilled hardware design engineer to drive the physical design of high-performance ASIC sub-chips for TPU architectures, from RTL to GDSII, with focus on timing, power, and area.

Join the AI and Infrastructure team to shape cutting-edge TPU hardware, collaborate with RTL, DFT, packaging teams, and partners, and contribute to Google's scalable AI platforms.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 10 years of experience in physical design, including full-chip or sub-chip implementation.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Skills

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Job description

Google LLC in Sunnyvale, CA is seeking a skilled hardware design engineer to drive the physical design of high-performance ASIC sub-chips for TPU architectures, from RTL to GDSII, with focus on timing, power, and area.

Join the AI and Infrastructure team to shape cutting-edge TPU hardware, collaborate with RTL, DFT, packaging teams, and partners, and contribute to Google's scalable AI platforms.