TPU RTL Design Engineer — AI/ML SoC Acceleration

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is pursuing breakthroughs in AI/ML hardware acceleration. As a SoC Design Engineer, you’ll contribute to RTL design and verification for TPU architecture within data center accelerators, shaping how AI workloads are powered at scale.

You’ll collaborate across architecture, power, DV, and physical design teams to deliver robust chips and infrastructure. The role emphasizes cross-functional leadership, rigorous design practices, and interaction with software and system hardware

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Responsibilities

• Learn more about benefits at Google .
• Work independently to create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

ASIC RTL design

SystemVerilog

Python/Tcl/Perl

EDA tools

clocking, reset, timing

Education

Bachelor's degree in Electrical Engineering/related field

Equivalent practical experience

Tools

EDA tools

Job description

Google is pursuing breakthroughs in AI/ML hardware acceleration. As a SoC Design Engineer, you’ll contribute to RTL design and verification for TPU architecture within data center accelerators, shaping how AI workloads are powered at scale.

You’ll collaborate across architecture, power, DV, and physical design teams to deliver robust chips and infrastructure. The role emphasizes cross-functional leadership, rigorous design practices, and interaction with software and system hardware