Senior RTL Design Engineer for TPU & AI/ML Hardware Equity

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking an experienced ASIC Design Engineer to help shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and its integration in AI/ML systems, designing RTL IP with a focus on management and control subsystems for datacenter accelerators.

You will collaborate across software and hardware teams, driving RTL development and verification for cutting-edge silicon used in Google's TPU technology.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages (e.g., Tcl, Python or Perl).

Responsibilities

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

ASIC design experience

SystemVerilog/RTL coding

Scripting languages (Tcl, Python or Pi

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

Job description

Google is seeking an experienced ASIC Design Engineer to help shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and its integration in AI/ML systems, designing RTL IP with a focus on management and control subsystems for datacenter accelerators.

You will collaborate across software and hardware teams, driving RTL development and verification for cutting-edge silicon used in Google's TPU technology.