TPU RTL Design Engineer - AI Accelerator Hardware

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Sunnyvale is seeking an RTL Design Engineer to help shape the future of AI/ML hardware acceleration. You will design high-performance, power-efficient TPU microarchitectures and SystemVerilog RTL blocks that power Google's AI workloads.

You will collaborate with Verification, Physical Design, and Firmware teams to ensure timing, area, and manufacturability while driving integration of on-chip networks across TPUs used in data centers.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 4 years of RTL design experience.
• Experience with digital design and microarchitecture design.
• Experience in design optimizing for performance, power, and area.
• Master's or PhD with emphasis on computer architecture (preferred).
• 5 years of RTL design experience (preferred).
• Experience with scripting languages (Python or Perl) (preferred).
• Experience with Linting, CDC, RDC, LEC (preferred).
• Experience architecting RTL solutions and ASIC synthesis flows (preferred).
• Cross-functional engagement with DV and PD teams (preferred).

Responsibilities

• Define TPU microarchitecture and develop SystemVerilog RTL code for complex digital designs.
• Partner with Verification teams to develop test plans, debug RTL, and support post-silicon validation.
• Collaborate with Physical Design to meet timing, area, power, and manufacturability requirements.
• Work with internal Partner teams to drive design integration across the ecosystem.

Skills

RTL design

Digital design

Microarchitecture design

Performance optimization

Cross-functional collaboration

Education

Bachelor's degree in EE, CE, CS or related field

Master's/PhD with computer architecture

Tools

Python

Perl

Linting

CDC/RDC/LEC

ASIC synthesis flows

Job description

Google Sunnyvale is seeking an RTL Design Engineer to help shape the future of AI/ML hardware acceleration. You will design high-performance, power-efficient TPU microarchitectures and SystemVerilog RTL blocks that power Google's AI workloads.

You will collaborate with Verification, Physical Design, and Firmware teams to ensure timing, area, and manufacturability while driving integration of on-chip networks across TPUs used in data centers.