TPU RTL Design Engineer – AI Hardware Architect

Careers; United States; Sur place; USD 163 000 - 236 000; Plein temps

Résumé du poste

Google Sunnyvale, CA is seeking an RTL Design Engineer for TPU architecture. You will design SystemVerilog RTL, define microarchitecture, and collaborate with software and system hardware teams to deliver scalable AI/ML accelerator IP.

The role emphasizes verification, timing closure, and integration within SoCs, with opportunities to influence TPU design and drive cutting-edge hardware innovations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• Experience with scripting languages.
• Master's degree or PhD with emphasis on computer architecture (preferred).
• 8 years of experience in ASIC design (preferred).
• Experience interacting with software, system hardware, and cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals (I2C, SPI, UART, etc.).
• Understanding of digital design fundamentals including synchronous/asynchronous logic, state machines and bus protocols.

Responsabilités

• Create and review management and control subsystem design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products per guidelines.
• Collaborate with architecture and power teams to evaluate features and impact.
• Work with DV teams to create test plans to verify and debug RTL.
• Coordinate with physical design teams to ensure timing closure.

Connaissances

RTL design

SystemVerilog

Digital design fundamentals

Cross-functional collaboration

Formation

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD in EE/CE/CS (preferred)

Description du poste

Google Sunnyvale, CA is seeking an RTL Design Engineer for TPU architecture. You will design SystemVerilog RTL, define microarchitecture, and collaborate with software and system hardware teams to deliver scalable AI/ML accelerator IP.

The role emphasizes verification, timing closure, and integration within SoCs, with opportunities to influence TPU design and drive cutting-edge hardware innovations.